This invention relates to the stacking of chips, or die, such as chips containing integrated circuitry.
In common assignee application Ser. No. 777,747, filed Dec. 21, 1996, U.S. Pat. No. 5,953,588 stackable IC chip layers were disclosed which permit chips having different functions and therefore different areas to be stacked as if they were same size chips, using stacking and electrical connection techniques and tools which have been developed for same size chips. The new units were referred to as "neo" (or "pseudo" or "virtual") chips. In addition to the advantage of being able to use chips of varying sizes in a given stack, that invention permits the processing and stacking of chips purchased as individual die, which are more readily available than chips purchased in wafer form. Furthermore, the chips purchased as individual die are generally "known good" die, which have been "burned in", and are therefore pre-tested prior to stacking.
As disclosed in the prior application, a re-wafering process is used, in which a neo-wafer is formed encapsulating known good chips, so that the chips can be prepared for stacking by covering their active surfaces with a dielectric layer, forming vias through the dielectric layer to reach the terminals on the respective chips, and metallizing to provide electrical connections from the chip terminals to side surfaces of the layer, which are created when the neo-wafer is diced, or sliced, to provide individual layers ready for stacking.
Prior to the invention of application Ser. No. 777,747, the extra steps required preparatory to stacking were sometimes carried out while the chips were still in their original wafer form. The wafer concept is almost universally used to simultaneously form integrated circuits (ICs) in numerous locations in the wafer, so that a multiplicity of separate IC chips will be created when the wafer is diced. Since preparation for stacking requires that the chip surfaces be metallized to connect their terminals to suitable access planes on the stack, manufacturing steps beyond the normal wafer processing steps are required, if stacking is intended. In some cases, chips in TSOP (packaged) form have been electrically connected to external circuitry by means of metal frames which are formed as part of the TSOP structure.
In the process disclosed in application Ser. No. 777,747, the chips which have been previously formed in a wafering process, and tested to insure their performance, need to be re-wafered, so they can be processed for subsequent stacking. Even in the case of a single chip, it is not feasible to perform the pre-stacking processing steps without using a neo-wafer, which proves a large enough body to permit efficient handling. Of course, the manufacturing process is much more cost effective if the neo-wafer contains a plurality of pre-formed, pre-tested chips which can be simultaneously prepared for stacking. The neo-wafer is subsequently diced to form individual layers ready for stacking. In effect, two wafering and dicing processes are used to facilitate stacking of chip-encapsulating layers.
As stated in the specification of application Ser. No. 777,747, the "primary challenge in using a neo-wafer containing multiple die is the accurate location of each die. *** With multiple die in the wafer, the accuracy necessary to locate each die prior to potting creates a potential alignment problem."